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publication# 14127 rev. i amendment /0 issue date: may 1995 advanced micro devices mach110-12/15/20 high-density ee cmos programmable logic final com'l: -12/15/20 ind: -14/18/24 distinctive characteristics n 44 pins n 32 macrocells n 12 ns t pd commercial 14 ns t pd industrial n 77 mhz f cnt n 38 inputs n 32 outputs n 32 flip-flops; 2 clock choices n 2 pal22v16 blocks n pin-compatible with mach111, mach210, mach211, mach215 general description the mach110 is a member of amd's high-performance ee cmos mach 1 family. this device has approxi- mately three times the logic macrocell capability of the popular pal22v10 without loss of speed. the mach110 consists of two pal blocks intercon- nected by a programmable switch matrix. the two pal blocks are essentially pal22v16 structures complete with product-term arrays and programmable macro- cells. the switch matrix connects the pal blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected pal blocks. this allows designs to be placed and routed efficiently. the mach110 macrocell provides either registered or combinatorial outputs with programmable polarity. if a registered configuration is chosen, the register can be configured as d-type or t-type to help reduce the number of product terms. the register type decision can be made by the designer or by the software. all macrocells can be connected to an i/o cell. if a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the i/o pin for use as an input.
amd 2 mach110-12/15/20 block diagram 44 x 70 and logic array and logic allocator 44 x 70 and logic array and logic allocator i/o 0 C i/o 15 i 0 C i 1, i 3 C i 4 i/o cells macrocells switch matrix macrocells i/o cells i/o 16 C i/o 31 clk 1 /i 5, clk 0 /i 2 14127i-1 16 16 16 16 22 22 16 16 16 16 2 4 2 2 2 oe oe
amd 3 mach110-12/15/20 connection diagram top view plcc 14127i-2 i/o 5 i/o 6 i/o 7 i 0 i 1 clk 0 /i 2 i/o 8 i/o 9 gnd i/o 10 i/o 11 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 gnd v cc i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 i 3 i 4 i/o 24 clk 1 /i 5 gnd i/o 23 i/o 22 i/o 21 i/o 12 i/o 13 i/o 14 v cc gnd i/o 16 i/o 15 i/o 17 i/o 18 i/o 19 i/o 20 7 8 9 10 11 12 13 15 16 14 17 5 61 32 4 4443424140 29 30 31 32 33 34 35 36 37 38 39 18 28 27 26 25 24 23 22 21 19 20 pin designations clk/i = clock or input gnd = ground i = input i/o = input/output v cc = supply voltage note: pin-compatible with mach111, mach210, mach211, and mach215.
amd mach110-12/15/20 (com'l) 4 ordering information commercial products valid combinations the valid combinations table lists configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. amd programmable logic products for commercial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: operating conditions c = commercial (0 c to +70 c) family type mach = macro array cmos high-speed speed -12 = 12 ns t pd -15 = 15 ns t pd -20 = 20 ns t pd mach110-12 MACH110-15 mach110-20 mach -12 j c valid combinations optional processing blank = standard processing 110 device number 110 = 32 macrocells, 44 pins package type j = 44-pin plastic leaded chip carrier (pl 044) jc
amd 5 mach110-14/18/25 (ind) ordering information industrial products valid combinations the valid combinations table lists configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. amd programmable logic products for industrial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: operating conditions i = industrial (C40 c to +85 c) family type mach = macro array cmos high-speed speed -14 = 14 ns t pd -18 = 18 ns t pd -24 = 24 ns t pd mach110-14 mach110-18 ji mach110-24 mach -14 i valid combinations optional processing blank = standard processing 110 device number 110 = 32 macrocells, 44 pins j package type j = 44-pin plastic leaded chip carrier (pl 044)
amd 6 mach110-12/15/20 functional description the mach110 consists of two pal blocks connected by a switch matrix. there are 32 i/o pins and 6 dedicated input pins feeding the switch matrix. these signals are distributed to the two pal blocks for efficient design implementation. there are two clock pins that can also be used as dedicated inputs. the pal blocks each pal block in the mach110 (figure 1) contains a 64-product-term logic array, a logic allocator, 16 macro- cells and 16 i/o cells. the switch matrix feeds each pal block with 22 inputs. this makes the pal block look effectively like an independent pal22v16. there are four additional output enable product terms in each pal block. for purposes of output enable, the 16 i/o cells are divided into 2 banks of 8 macrocells. each bank is allocated two of the output enable product terms. an asynchronous reset product term and an asynchro- nous preset product term are provided for flip-flop initialization. all flip-flops within the pal block are initialized together. the switch matrix the mach110 switch matrix is fed by the inputs and feedback signals from the pal blocks. each pal block provides 16 internal feedback signals and 16 i/o feedback signals. the switch matrix distributes these signals back to the pal blocks in an efficient manner that also provides for high performance. the design software automatically configures the switch matrix when fitting a design into the device. the product-term array the mach110 product-term array consists of 64 product terms for logic use, and 6 special-purpose product terms. four of the special-purpose product terms provide programmable output enable, one provides asynchronous reset, and one provides a synchronous preset. two of the output enable product terms are used for the first eight i/o cells; the other two control the last eight macrocells. the logic allocator the logic allocator in the mach110 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. each macrocell can be driven by up to 12 product terms. the design software automatically configures the logic allocator when fitting the design into the device. table 1 illustrates which product term clusters are available to each macrocell within a pal block. refer to figure 1 for cluster and macrocell numbers. table 1. logic allocation available output macrocell clusters m 0 c 0 , c 1 m 1 c 0 , c 1 , c 2 m 2 c 1 , c 2 , c 3 m 3 c 2 , c 3 , c 4 m 4 c 3 , c 4 , c 5 m 5 c 4 , c 5 , c 6 m 6 c 5 , c 6 , c 7 m 7 c 6 , c 7 m 8 c 8 , c 9 m 9 c 8 , c 9 , c 10 m 10 c 9 , c 10 , c 11 m 11 c 10 , c 11 , c 12 m 12 c 11 , c 12 , c 13 m 13 c 12 , c 13 , c 14 m 14 c 13 , c 14 , c 15 m 15 c 14 , c 15 the macrocell the mach110 macrocells can be configured as either registered or combinatorial, with programmable polar- ity. the macrocell provides internal feedback whether configured as registered or combinatorial. the flip-flops can be configured as d-type or t-type, allowing for product-term optimization. the flip-flops can individually select one of two clock pins, which are also available as data inputs. the regis- ters are clocked on the low-to-high transition of the clock signal. the flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms. the i/o cell the i/o cell in the mach110 consists of a three-state output buffer. the three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. if product term control is chosen, one of two product terms may be used to provide the control. the two product terms that are available are common to eight i/o cells. within each pal block, two product terms are available for selection by the first eight three-state outputs; two other product terms are available for selection by the last eight three-state outputs. these choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus.
amd 7 mach110-12/15/20 14127i-3 0 4 8 12 16 20 24 28 40 32 43 36 0 4 8 12 16 20 24 28 40 32 43 36 i/o cell i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o switch matrix output enable output enable asynchronous reset asynchronous preset output enable output enable clk 16 i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell 16 output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell 4 0 logic allocator 63 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 m 3 m 6 m 5 m 4 m 2 m 1 m 0 m 9 m 8 m 7 m 10 m 11 m 12 m 13 m 14 m 15 figure 1. mach110 pal block
amd mach110-12/15/20 (com'l) 8 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied -55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground -0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage -0.5 v to v cc + 0.5 v . . . . . . . . . . . . dc output or i/o pin voltage -0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . latchup current (t a = 0 c to 70 c) 200 ma . . . . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. pro gramming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +70 c . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . operating ranges define those limits between which the func tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = C3.2 ma, v cc = min 2.4 v v in = v ih or v il v ol output low voltage i ol = 16 ma, v cc = min 0.5 v v in = v ih or v il v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) i ih input high current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low current v in = 0 v, v cc = max (note 2) -10 m a i ozh offstate output leakage v out = 5.25 v, v cc = max 10 m a current high v in = v ih or v il (note 2) i ozl offstate output leakage v out = 0 v, v cc = max -10 m a current low v in = v ih or v il (note 2) i sc output shortcircuit current v out = 0.5 v, v cc = max (note 3) -30 -160 ma i cc supply current (typical) v cc = 5 v, t a =25 c, 95 ma f = 25 mhz (note 4) notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. measured with a 16-bit up/down counter program. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset.
amd 9 mach110-12/15/20 (com'l) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c6 pf c out output capacitance v out = 2.0 v f = 1 mhz 8 pf switching characteristics over commercial operating ranges (note 2) parameter symbol parameter description min max min max min max unit t pd input, i/o, or feedback to combinatorial 12 15 20 ns output (note 3) 71013ns 81114ns t h hold time 0 0 0 ns t co clock to output (note 3) 8 10 12 ns t wl 668ns t wh 668ns 66.7 50 40 mhz 62.5 47.6 38.5 mhz f max 76.9 66.6 47.6 mhz 71.4 55.5 43.5 mhz no feedback 1/(t wl + t wh ) 83.3 83.3 62.5 mhz t ar asynchronous reset to registered output 16 20 25 ns t arw asynchronous reset width (note 1) 12 15 20 ns t arr asynchronous reset recovery time (note 1) 8 10 15 ns t ap asynchronous preset to registered output 16 20 25 ns t apw asynchronous preset width (note 1) 12 15 20 ns t apr asynchronous preset recovery time (note 1) 8 10 15 ns t ea input, i/o, or feedback to output enable (note 3) 12 15 20 ns t er input, i/o, or feedback to output disable (note 3) 12 15 20 ns notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. see switching test circuit, for test conditions. 3. parameters measured with 16 outputs switching. setup time from input, i/o, or feedback to clock -12 -20 clock width d-type t-type d-type t-type low high d-type t-type maximum frequency (note 1) external feedback 1/(t s + t co ) internal feedback (f cnt ) t s -15
amd mach110-14/18/20 (ind) 10 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied -55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground -0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage -0.5 v to v cc + 0.5 v . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . latchup current (t a = C40 c to +85 c) 200 ma . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. industrial operating ranges ambient temperature (t a ) operating in free air C40 c to +85 c . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.5 v to +5.5 v . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over industrial operating ranges unless otherwise specified parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = C3.2 ma, v cc = min 2.4 v v in = v ih or v il v ol output low voltage i ol = 16 ma, v cc = min 0.5 v v in = v ih or v il v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) i ih input high current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low current v in = 0 v, v cc = max (note 2) C10 m a i ozh off-state output leakage v out = 5.25 v, v cc = max 10 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0 v, v cc = max C10 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C160 ma supply current (typical) v cc = 5 v, t a = 25 c, f = 25 mhz (note 4) 95 ma notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. measured with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset. i cc
amd 11 mach110-14/18/20 (ind) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c6pf c out output capacitance v out = 2.0 v f = 1 mhz 8 pf switching characteristics over industrial operating ranges (note 2) parameter symbol parameter description min max min max min max unit t pd input, i/o, or feedback to combinatorial 14.5 18 24 ns output (note 3) 8.5 12 16 ns 10 13.5 17 ns t h hold time 0 0 0 ns t co clock to output (note 3) 10 12 14.5 ns t wl 7.5 7.5 10 ns t wh 7.5 7.5 10 ns 53.5 40 32 mhz 50 38 30 mhz f max 61.5 53 38 mhz 57 44 34.5 mhz no feedback 1/(t wl + t wh ) 66.5 66.5 50 mhz t ar asynchronous reset to registered output 19.5 24 30 ns t arw asynchronous reset width (note 1) 14.5 18 24 ns t arr asynchronous reset recovery time (note 1) 10 12 18 ns t ap asynchronous preset to registered output 19.5 24 30 ns t apw asynchronous preset width (note 1) 14.5 18 24 ns t apr asynchronous preset recovery time (note 1) 10 12 18 ns t ea input, i/o, or feedback to output enable (note 3) 14.5 18 24 ns t er input, i/o, or feedback to output disable (note 3) 14.5 18 24 ns notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. see switching test circuit, for test conditions. 3. parameters measured with 16 outputs switching. setup time from input, i/o, or feedback to clock -14 -24 clock width d-type t-type d-type t-type low high d-type t-type maximum frequency (note 1) external feedback 1/(t s + t co ) internal feedback (f cnt ) t s -18
amd 12 mach110-12/15/20 typical current vs. voltage (i-v) characteristics v cc = 5.0 v, t a = 25 c input 20 C40 C60 C80 C2 C1 123 output, high i i (ma) v i (v) C20 i oh (ma) v oh (v) 25 C50 C75 C100 C3 C2 C1 123 C25 C125 C150 45 45 C100 C0.8 C0.6 C0.4 .2 C0.2 C1.0 14127i-4 output, low .4 .6 1.0 .8 60 40 20 C20 C40 80 C60 C80 i ol (ma) v ol (v) 14127i-5 14127i-6
amd 13 mach110-12/15/20 typical i cc characteristics v cc = 5 v, t a = 25 c 14127i-7 mach110 150 125 100 75 50 25 0 0 10203040 5060708090 i cc (ma) frequency (mhz) the selected typical pattern is a 16-bit up/down counter. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset. maximum frequency shown uses internal feedback and a d-type register.
amd 14 mach110-12/15/20 typical thermal characteristics measured at 25 c ambient. these parameters are not tested. parameter symbol parameter description plcc unit q jc thermal impedance, junction to case 14 c/w q ja thermal impedance, junction to ambient 39 c/w q jma thermal impedance, junction to 200 lfpm air 33 c/w 400 lfpm air 30 c/w 600 lfpm air 27 c/w 800 lfpm air 25 c/w plastic q jc considerations the data listed for plastic q jc are for reference only and are not recommended for use in calculating junction temperatures. the heat-flow paths in plastic-encapsulated devices are complex, making the q jc measurement relative to a specific location on the package surface. tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. furthermore, q jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. therefore, the measurements can only be used in a similar environment. typ ambient with air flow
amd 15 mach110-12/15/20 switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 nsC4 ns typical. t pd input, i/o, or feedback combinatorial output v t v t combinatorial output v t input, i/o, or feed- back registered output registered output t s t co v t t h v t clock t wh clock clock width t wl v t combinatorial output registered input (mach 2 and 4) t sir t ico v t t hir v t input register clock registered input latched output (mach 2, 3, and 4) gate gate width (mach 2, 3, and 4) t gws v t v t v t v t t ics input register to output register setup (mach 2 and 4) output register clock input register clock registered input t pdl input, i/o, or feedback latched out gate v t t hl t sl t go v t v t 14127i-8 14127i-9 14127i-10 14127i-11 14127i-12 14127i-13 14127i-14
amd 16 mach110-12/15/20 switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 nsC4 ns typical. latched input (mach 2 and 4) latched input and output (mach 2, 3, and 4) latched in output latch gate latched out t sll combinatorial output gate t hil t sil t igo latched in t pdll t igol t igs input latch gate v t v t v t v t v t v t 14127i-15 14127i-16
amd 17 mach110-12/15/20 switching waveforms t wich clock input register clock width (mach 2 and 4) v t t wicl v t v t t arw v t t ar asynchronous reset input, i/o, or feedback registered output clock t arr asynchronous preset registered output clock v t v t outputs output disable/enable t er t ea v oh - 0.5v v ol + 0.5v notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 nsC4 ns typical. input, i/o, or feedback v t v t input, i/o, or feedback t apw v t t ap t apr input latch gate input latch gate width (mach 2 and 4) t wigl v t 14127i-17 14127i-18 14127i-19 14127i-20 14127i-21
amd 18 mach110-12/15/20 key to switching waveforms ks000010-pal must be steady may change from h to l may change from l to h does not apply don't care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs switching test circuit measured specification s 1 c l r 1 r 2 output value t pd , t co closed 1.5 v t ea z ? h: open 35 pf 1.5 v z ? l: closed 300 w 390 w t er h ? z: open 5 pf h ? z: v oh C 0.5 v l ? z: closed l ? z: v ol + 0.5 v commercial 14127i-22 c l output r 1 r 2 s 1 test point 5 v *switching several outputs simultaneously should be avoided for accurate measurement.
amd 19 mach110-12/15/20 f max parameters the parameter f max is the maximum clock rate at which the device is guaranteed to operate. because the flexi- bility inherent in programmable logic devices offers a choice of clocked flip-flop designs, f max is specified for three types of synchronous designs. the first type of design is a state machine with feedback signals sent off-chip. this external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. the slowest path defining the period is the sum of the clock-to-output time and the in- put setup time for the external signals (t s + t co ). the re- ciprocal, f max , is the maximum frequency with external feedback or in conjunction with an equivalent speed de- vice. this f max is designated f max external. the second type of design is a single-chip state ma- chine with internal feedback only. in this case, flip-flop inputs are defined by the device inputs and flip-flop out- puts. under these conditions, the period is limited by the internal delay from the flip-flop outputs through the inter- nal feedback and logic to the flip-flop inputs. this f max is designated f max internal. a simple internal counter is a good example of this type of design; therefore, this pa- rameter is sometimes called f cnt. the third type of design is a simple data path applica- tion. in this case, input data is presented to the flip-flop and clocked through; no feedback is employed. under these conditions, the period is limited by the sum of the data setup time and the data hold time (t s + t h ). however, a lower limit for the period of each f max type is the mini- mum clock period (t wh + t wl ). usually, this minimum clock period determines the period for the third f max , des- ignated f max no feedback. for devices with input registers, one additional f max pa- rameter is specified: f maxir . because this involves no feedback, it is calculated the same way as f max no feed- back. the minimum period will be limited either by the sum of the setup and hold times (t sir + t hir ) or the sum of the clock widths (t wicl + t wich ). the clock widths are nor- mally the limiting parameters, so that f maxir is specified as 1/(t wicl + t wich ). note that if both input and output reg- isters are use in the same path, the overall frequency will be limited by t ics . all frequencies except f max internal are calculated from other measured ac parameters. f max internal is meas- ured directly. t hir t sir logic register tt clk (second chip) sco t s f max external; 1/(t s + t co ) logic register clk f max internal (f cnt ) logic register t clk s f max no feedback; 1/(t s + t h ) or 1/(t wh + t wl ) 14127i-23 logic register clk f maxir ; 1/(t sir + t hir ) or 1/(t wicl + t wich )
amd 20 mach110-12/15/20 endurance characteristics the mach families are manufactured using amd's advanced electrically erasable process. this technol- ogy uses an ee cell to replace the fuse link used in bipolar parts. as a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. endurance characteristics parameter symbol parameter description min units test conditions 10 years max storage temperature 20 years max operating temperature n max reprogramming cycles 100 cycles normal programming conditions t dr min pattern data retention time
amd 21 mach110-12/15/20 input/output equivalent schematics input i/o preload circuitry esd protection feedback input v cc v cc 1 k w 100 k w v cc v cc 100 k w 1 k w 14127i-24
amd 22 mach110-12/15/20 power-up reset the mach devices have been designed with the capa- bility to reset during system power-up. following power- up, all flip-flops will be reset to low. the output state will depend on the logic polarity. this feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. a timing dia- gram and parameter table are shown below. due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to insure a valid power-up reset. these conditions are: 1. the v cc rise must be monotonic. 2. following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. parameter symbol parameter descriptions max unit t pr power-up reset time 10 m s t s input or feedback setup time t wl clock width low see switching characteristics t pr t wl t s 4 v v cc power registered output clock 14127i-25 power-up reset waveform
amd 23 mach110-12/15/20 using preload and observability in order to be testable, a circuit must be both controllable and observable. to achieve this, the mach devices incorporate register preload and observability. in preload mode, each flip-flop in the mach device can be loaded from the i/o pins, in order to perform functional testing of complex state machines. register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. this ability to control the mach device's internal state can shorten test sequences, since it is easier to reach the state of interest. the observability function makes it possible to see the internal state of the buried registers during test by overriding each register's output enable and activating the output buffer. the values stored in output and buried registers can then be observed on the i/o pins. without this feature, a thorough functional test would be impossible for any designs with buried registers. while the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. one case involves asynchronous reset and preset. if the mach registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. this is illustrated in figure 2. care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. another case to be aware of arises in testing combinato- rial logic. when an output is configured as combinato- rial, the observability feature forces the output into registered mode. when this happens, all product terms are forced to zero, which eliminates all combinatorial data. for a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. if the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in figure 3. as this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. to insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. all mach 2 devices support both preload and observability. contact individual programming vendors in order to verify programmer support. ar figure 2. preload/reset conflict q 1 on off preload mode q 2 ar preloaded high d q q 1 d q ar preloaded high q 2 14127i-26 figure 3. combinatorial latch set reset 14127i-27
amd 24 mach110-12/15/20 development systems (subject to change) for more information on the products listed below, please consult the amd fusionpld catalog. manufacturer software development systems advanced micro devices, inc. p.o. box 3453, ms 1028 sunnyvale, ca 94088-3543 (800) 222-9323 or (408) 732-2400 advanced micro devices, inc. p.o. box 3453, ms 1028 sunnyvale, ca 94088-3543 (800) 222-9323 or (408) 732-2400 advanced micro devices, inc. p.o. box 3453, ms 1028 sunnyvale, ca 94088-3543 (800) 222-9323 or (408) 732-2400 advanced micro devices, inc. p.o. box 3453, ms 1028 sunnyvale, ca 94088-3543 (800) 222-9323 or (408) 732-2400 cadence design systems 555 river oaks pkwy san jose, ca 95134 (408) 943-1234 capilano computing 960 quayside dr., suite 406 new westminster, b.c. canada v3m 6g2 (800) 444-9064 or (604) 552-6200 cina, inc. p.o. box 4872 mountain view, ca 94040 (415) 940-1723 data i/o corporation 10525 willows road n.e. p.o. box 97046 redmond, wa 98073-9746 (800) 332-8246 or (206) 881-6444 int gmbh busenstrasse 6 d-8033 martinsried, munich, germany (89) 857-6667 isdata gmbh daimlerstr. 51 d7500 karlsruhe 21 germany germany: 0721/75 10 87 u.s.: (510) 531-8553 logic modeling 19500 nw gibbs dr. p.o. box 310 beaverton, or 97075 (503) 690-6900 logical devices, inc. 692 s. military trail deerfield beach, fl 33442 (800) 331-7766 or (305) 428-6868 machxl a software ver. 2.0 composerpic tm designer (requires mach fitter) verilog, leapfrog, rapidsim simulators (models also available from logic modeling) ver. 3.3 log/ic tm software (requires mach fitter) abel tm -5 software (requires mach fitter) synario tm software macabel tm software (requires smartpart mach fitter) amd-abel software data i/o mach fitters prodeveloper/amd software prosynthesis/amd software design center/amd software smartmodel a library smartcat circuit analyzer pldsim 90 cupl tm software
amd 25 mach110-12/15/20 manufacturer test generation system acugen software, inc. 427-3 amherst st., suite 391 nashua, nh 03063 (603) 891-1995 int gmbh busenstrasse 6 d-8033 martinsried, munich, germany (87) 857-6667 development systems (subject to change) (continued) advanced micro devices is not responsible for any information relating to the products of third parties. the inclusion of such information is not a representation nor an endorsement by amd of these products. atgen tm test generation software multisim interactive simulator lasar pldcheck 90 manufacturer software development systems mentor graphics corp. 8005 s.w. boeckman rd. wilsonville, or 97070-7777 (800) 547-3000 or (503) 685-7000 microsim corp. 20 fairbanks irvine, ca 92718 (714) 770-3022 minc incorporated 6755 earl drive, suite 200 colorado springs, co 80918 (800) 755-fpga or (719) 590-1155 orcad 3175 n.w. aloclek dr. hillsboro, or 97124 (503) 690-9881 susieCcad 10000 nevada highway, suite 201 boulder city, nv 89005 (702) 293-2271 teradyne eda 321 harrison ave. boston, ma 02118 (800) 777-2432 or (617) 422-2793 viewlogic systems, inc. 293 boston post road west marlboro, ma 01752 (800) 442-4660 or (508) 480-0881 programmable logic design tools 386+ schematic design tool 386+ digital simulation tools viewpld or propld (requires prosim simulator mach fitter) viewsim simulator (models for viewsim also available from logic modeling) pldesigner tm -xl software (requires mach fitter) pldsynthesis tm (requires mach fitter) quicksim simulator (models also available from logic modeling) design center software (requires mach fitter) susie tm simulator
amd 26 mach110-12/15/20 approved programmers (subject to change) for more information on the products listed below, please consult the amd fusionpld catalog. manufacturer programmer configuration advin systems, inc. 1050-l east duane ave. sunnyvale, ca 94086 (408) 243-7000 bp microsystems 100 n. post oak rd. houston, tx 77055-7237 (800) 225-2102 or (713) 688-4600 data i/o corporation 10525 willows road n.e. p.o. box 97046 redmond, wa 98073-9746 (800) 332-8246 or (206) 881-6444 logical devices inc./digelec 692 s. military trail deerfield beach, fl 33442 (800) 331-7766 or (305) 428-6868 sms north america, inc. 16522 ne 135th place redmond, wa 98052 (800) 722-4122 or sms lm grund 15 d-7988 vangen im allgau, germany 07522-5018 stag microsystems inc. 1600 wyatt dr. suite 3 santa clara, ca 95054 (408) 988-1118 or stag house martinfield, welwyn garden city herfordshire uk al7 1jt 707-332148 system general 510 s. park victoria dr. milpitas, ca 95035 (408) 263-6667 or 3f, no. 1, alley 8, lane 45 bao shing rd., shin diau taipei, taiwan 2-917-3005 bp1200 pilot u84 model 3900 turpro-1 unisite tm autosite stag quazar sprint/expert allpro tm C88 manufacturer programmer configuration corelis, inc. 12607 hidden creek way, suite h cerritos, california 70703 (310) 926-6727 advanced micro devices p.o. box 3453, ms-1028 sunnyvale, ca 94088-3453 (800) 222-9323 machpro jtag prog approved on-board programmers
amd 27 mach110-12/15/20 programmer socket adapters (subject to change) manufacturer part number edi corporation p.o. box 366 patterson, ca 95363 (209) 892-3270 emulation technology 2344 walsh ave., bldg. f santa clara, ca 95051 (408) 982-0660 logical systems corp. p.o. box 6184 syracuse, ny 13217-6184 (315) 478-0722 procon technologies, inc. 1333 lawrence expwy, suite 207 santa clara, ca 95051 (408) 246-4456 contact manufacturer contact manufacturer contact manufacturer contact manufacturer
amd 28 mach110-12/15/20 physical dimensions* pl 044 44-pin plastic leaded chip carrier (measured in inches) top view seating plane .685 .695 .650 .656 pin 1 i.d. .685 .695 .650 .656 .026 .032 .050 ref .042 .056 .062 .083 .013 .021 .590 .630 .500 ref .009 .015 .165 .180 .090 .120 16-038-sq pl 044 da78 6-28-94 ae side view *for reference only. bsc is an ansi standard for basic space centering. trademarks copyright ? 1995 advanced micro devices, inc. all rights reserved. amd, the amd logo, mach, and pal are registered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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